1. Field of the Invention
The present invention generally relates to clock generators. More specifically, the present invention provides a frequency-locked clock generator having improved jitter and updating performance for large divider ratios.
2. Related Art
Often, a phase-locked loop (PLL) is used to generate an output clock signal from a given input signal having a reference frequency. The frequency of the output signal compared to the frequency of the input signal is considered the divider ratio of the PLL. The reference input signal is generally a relatively low frequency signal generated by an expensive crystal oscillator.
The loop bandwidth of the PLL is limited by the frequency of the input reference signal. Consequently, the updating performance of the PLL is impaired when a low frequency reference signal is used to generate a high frequency clock signal. Specifically, for large divider ratios, the limited loop bandwidth may prevent adequate updating of the output clock signal. In turn, the jitter performance of the PLL suffers. Overall, the PLL is an expensive design that provides poor performance in terms of slow response/updating time and jitter control when used to generate a high frequency output clock signal from a low frequency input signal.